A Histogram BIST Scheme for ADCs Based on Time Decomposition and Space Decomposition

This paper proposes a histogram BIST scheme for ADC static testing. This scheme makes use of time decomposition technique and space decomposition technique. The traditional ADC BIST approach based on time decomposition technique can reduce the test hardware overhead, however it will typically produce large testing time. For a monotonic ADC, the output codes have an approximate proportional relationship to the input signal. By utilizing this property, a space decomposition technique is proposed to reduce the testing time. By combining these two techniques, ADC’s static parameters can be estimated, including INL, DNL, offset and gain, in shorter test time with low hardware overhead. The proposed BIST scheme has been verified by simulation and the test results have been compared with those obtained from Verigy SOC 93000.